An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors
نویسندگان
چکیده
Power Compiler: A Gate-Level Power Optimization and Synthesis System p. 74 Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy p. 82 Design Optimization for High-Speed Per-address Two-level Branch Predictors p. 88 PA-8000: A Case Study of Static and Dynamic Branch Prediction p. 97 Discrete Drive Selection for Continuous Sizing p. 110 Continuous Retiming: Algorithms and Applications p. 116 Optimal Clock Period Clustering for Sequential Circuits with Retiming p. 122 Comparison between nMOS Pass-Transistor logic style vs. CMOS Complementary Cells p. 130 Circuit-Based Description and Modeling of Electromagnetic Noise Effects in Packaged Low-Power Electronics p. 136
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What is Physical Synthesis?
VLSI technology scaling has caused interconnect delay to increasingly dominate the overall chip performance. A design that satisfies timing constraints after logic synthesis will not necessarily meet timing constraints after place-androute due to wire delays. Physical synthesis has been emerged as a necessary weapon for design closure. It is a core component of modern VLSI design methodologies ...
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